COMP.CE.250 System-on-Chip Design
Welcome to the course! To get started you will find information from
- Moodle page for group formation and course news
- Course GitLab
- COMP.CE.250 Mattermost channel for discussion
- If you're new to Mattermost, sign up using this invite link
- This site for all the rest - please take the time to read everything carefully
- Material and exercise pages will gradually be added and open as the course progresses!
Weekly Events
- Lectures: Wed 14:15-16:00 in TB206
- Remote participation possible in Zoom: https://tuni.zoom.us/j/63468637658?pwd=hYNZ3mnPoIP94Z36QIV2erLO2sALbw.1
- Exercises: Mon 14:15-16:00 and Thu 14:15-16:00 in TC217 (starting from 26.1.)
Course news
Course Schedule
| wk | dates | lecture Wed 14-16 | exercise Mon 14-16 and Thu 14-16 | deadline |
| 3 | 12.1. - 18.1. | Course info | ||
| 4 | 19.1. - 25.1. | SystemVerilog for Design | ||
| 5 | 26.1. - 1.2. | SoC Survey | SoC Survey | |
| 6 | 2.2. - 8.2. | Computer Architecture for System-on-Chip Design |
Introduction to SystemVerilog | |
| 7 | 9.2. - 15.2. | Interconnects | Ex0: Didactic SoC hands-on | |
| 8 | 16.2. - 22.2. | Exercise Project Introduction & Practical SoC Development |
Exercises | |
| 9 | 23.2. - 1.3. | |||
| 10 | 2.3. - 8.3. | Special Topic | Exercises | |
| 11 | 9.3. - 15.3. | Special Topic | Exercises | |
| 12 | 16.3. - 22.3. | Special Topic | Exercises | |
| 13 | 23.3. - 29.3. | Special Topic | Exercises | |
| 14 | 30.3. - 5.4. | Easter 1. - 7.4. | Easter 1. - 7.4. | |
| 15 | 6.4. - 12.4. | Special Topic | Exercises | |
| 16 | 13.4. - 19.4. | Special Topic | Exercises | |
| 17 | 20.4 - 26.4. | Wrap up | 3: Adv | |
| 18 19 |
27.4. - 10.5. | |||
FPGA lab not in use on Thu 22.1.
The FPGA lab is reserved for another event on Thu 22.1.
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0 / 0 General Information
Wednesday, 7 January 2026, 00:01 – Monday, 7 January 2036, 00:01
Course grading: Sum of SoC Project (max 50) and exam (max 50):
- 50p -> 1
- 60p -> 2
- 70p -> 3
- 80p -> 4
- 90p -> 5
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1 Exercises: Setting up the Virtual Machine in TC217 | |||
| 2 Git Primer | |||
| 3 NDA Agreement: FPGA lab access | SystemVerilog Intro | 0 / 1 | 0 / 0 |
0 / 0 Lectures
Wednesday, 14 January 2026, 14:01 – Monday, 14 January 2036, 14:01
1 points required to pass the module.
Lecture materials for the course are presented here. New slides will be added before each lecture.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1 Introduction | |||
| 2 SystemVerilog | |||
0 / 1 SoC Survey
Wednesday, 14 January 2026, 00:01 – Thursday, 29 January 2026, 23:58
Late submissions are allowed until Sunday, 22 February 2026, 23:59.
Task: Summarize the contents of a GitHub repository assigned to your group. Report your findings in a 5-10 minute presentation: 2-3 Powerpoint slides are enough.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1 SoC Survey | SoC Survey | 0 / 9 | 0 / 1 |
0 / 1 Introduction to SystemVerilog
Monday, 19 January 2026, 00:01 – Sunday, 8 February 2026, 23:58
Late submissions are allowed until Sunday, 22 February 2026, 23:59.
This optional exercise aims to introduce the basic design capabilities of SystemVerilog language.
- The design oriented properties of SystemVerilog language
- Combinational design
- Synchronous design
- Simple testbenches to support simulation
This exercise will not affect your grade. If you are taking SoC Verification, doing it again on this course is not required.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 0 Simulation environment | SystemVerilog Intro | 0 | 0 / 0 |
| 1 Combinational design with SystemVerilog | SystemVerilog Intro | 0 | 0 / 0 |
| 2 Synchronous design with SystemVerilog | SystemVerilog Intro | 0 | 0 / 0 |
| 3 Simple testbenches | SystemVerilog Intro | 0 / 9 | 0 / 1 |
| 4 State machines | SystemVerilog Intro | 0 | 0 / 0 |
| 5 Common cells | SystemVerilog Intro | 0 | 0 / 0 |
SoC Survey
0 / 1
SystemVerilog Intro
0 / 1