Monday, 19 January 2026, 00:01 – Sunday, 8 February 2026, 23:58
Late submissions are allowed until Sunday, 22 February 2026, 23:59.

This optional exercise aims to introduce the basic design capabilities of SystemVerilog language.

1. The design oriented properties of SystemVerilog language
2. Combinational design
3. Synchronous design
4. Simple testbenches to support simulation

This exercise will not affect your grade. If you are taking SoC Verification, doing it again on this course is not required.

• 0 Simulation environment
• 1 Combinational design with SystemVerilog
• 2 Synchronous design with SystemVerilog
• 3 Simple testbenches
• 4 State machines
• 5 Common cells