Objectives

This exercise will introduce basic concepts of SystemVerilog as design language:

1. Hello world module
2. Simulation with Questa

Instructions

The focus in this exercise is to verify the build environment.

Preparing the environment

The simulations in the exercises are run with the Linux build of Questa, so the first task is to configure and start a virtual machine:

• VMWare instructions
• Start the terminal
• Before you can compile and simulate your code you need to add the used tools to your environment path:

$ source /opt/questa/questa.sh 

• Note that this sets the path variable for the current session only, so this has to be done every time you start the terminal



Git repositories

We have two git repositories on the course: the group repository and a personal one. These files are found in the personal repository.

You can still do this as a group: just decide whose repository you will use.

• Clone your git repository
• Navigate to folder ex_systemverilog in your repository
• Create a library for the project with:

$ vlib sv_ex_lib           # Create your own design library ...
$ vmap work $PWD/sv_ex_lib # ... and map it as 'work'

• Then you can compile and run the simulation with:

$ vlog hello.sv
$ vsim -do "run -all" -c hello

• the -c flag starts the simulation in console without the GUI