Objectives

This exercise will introduce basic concepts of SystemVerilog as design language:

1. Declaring modules in Verilog way
2. Combinational design using SystemVerilog
3. Simulation with a .do file

Instructions

The focus in this exercise is to get familiar with the structure and syntax of the SystemVerilog language with a basic combinational example design.

When the simulation environment has been tested it's time to start the first SystemVerilog design. Let's make an asynchronous adder.

• Create a file adder.sv
• Start by declaring a module called adder:

module adder (operand_a_in,operand_b_in,carry_out,result_out);

• Include all the input and output ports of the module in the declaration
• This design takes in two operands and adds them together to the result output
• The signal carry_out is the ninth output bit


• Declare ports as inputs or outputs:

// Inputs
input [7:0] operand_a_in;
input [7:0] operand_b_in;
// Outputs
output carry_out;
output [7:0] result_out;

• Add functionality
• When ready, end the module with

endmodule: adder

assign signal_a = signal_b;

assign {bit_a, bit_b} = 2'b01;

assign bit_a = 1'b0;
assign bit_b = 1'b1;

• Compile the design as you did for the hello module
• Simulate with:

$ vsim -do sim/adder.do adder