Objectives

This exercise will introduce basic concepts of SystemVerilog as design language:

1. Declaring modules in SystemVerilog way
2. RTL design using SystemVerilog
3. Using a testbench for simulation

Instructions

Next, let's improve the design by making it synchronous and capable of subtraction as well.

• Create a file adder_synch.sv and declare a new adder_synch module in it
• The module declaration in the previous example was a pretty legacy (but quite common nonetheless) way of doing things and had unwanted redundancy because the ports had to be declared in two places - first in the port list and then declared as input or output.
• SystemVerilog has improvements in this so that the port directions and data types can be declared directly in the port list. It's recommended, because redundancy always introduces a change for bugs.
• Also, using parameters for signal widths is recommended
• So, a better way to declare the module would be:

module adder_synch #(parameter data_width_g = 8) (
    input [data_width_g-1:0] operand_a_in,
    input [data_width_g-1:0] operand_b_in,
    output logic [data_width_g-1:0] result_out,
    output logic carry_out
    );

• As we want to make the adder synchronous, we need clock and reset signals. Add inputs clk and rst_n to your module
• As we want to add the subtraction capability, also add a 1-bit input add_sub to your module

• Add an always_ff procedure that is sensitive to negative edge of rst_n or positive edge of clk. This results in a synchronized procedure with asynchronous reset.

always_ff @(posedge clk or negedge rst_n) begin 
	...
end

• Handle reset (active low) and normal operation in an if-clause:

if (~rst_n) begin
    ...
end
else begin
    ...
end

• Fill in the functionality. Do an addition or subtraction based on the add_sub signal
• When add_sub = 1, an addition is performed
• Remember to clear all output registers on reset

Test with vlog that your design compiles. In the next exercise you will create a simple testbench for simulation.