Objectives

This exercise will introduce basic concepts of SystemVerilog as design language:

1. State Machines

Instructions

• Start by declaring a new module fsm and add a synchronous always_ff block as you did in the synchronous adder
• The module should have a clock and asynchronous active-low reset inputs, but you can decide the rest of the inputs and outputs yourself
• Add enumerated variables for the current and next state, for exmple:

typedef enum int unsigned { IDLE = 1, WRITE = 2, ACK = 4} state_t; // verbose: one-hot encoding
state_t state, next_state;

// OR:
enum { IDLE, WRITE, ACK } state, next_state; // less verbose

• Decide the states yourself
• Note that enumeration is a SystemVerilog addition: not supported by Verilog compilers
• You can declare your state machine in 1-3 procedures:
• A single always_ff block: for simple state machines, but bigger FSMs get complex
• always_ff for state transitions + always_comb for next state and ouput logic: usually preferred
• always_ff for state transitions + separate always_comb blocks for next state and ouput logic
• a case structure is very useful for next state logic

Experiment with your code.

• Finally: write a simple testbench for simulating your state machine

Exercise returns

None