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Objectives
This exercise will introduce basic concepts of SystemVerilog as design language:
Code examples
Instructions
The Pulp project has a repository containing common SystemVerilog components, such as clock and reset synchronizers, counters, and data path elements, for example decoders and FIFOs.
Between sessions you lose the "sourced" paths so if you get an error that the run script cannot find the compiler/simulator run the sourcing script as before
Always comment what you're doing in the code! Commenting in SystemVerilog works as in C/C++ i.e. // or /* ... */
Remember to indent the code and use descriptive variable/class names (as in the given code package or some other sensible way..), readibility is nice.