COMP.CE.510 Chip Implementation

Welcome to the course! To get started you will find information from

Plussa (This site!): Material, exercises, deadlines, exercise submissions
Moodle: Exercise group formation
Course GitLab: Git repositories for computer exercises
Mattermost: course channel for semi real-time chat (with staff and other students): COMP.CE.510 Chip Implementation

Note: This is not accessible by intra credentials, but you'll have to create your own account with your university email.

Starting lecture in TC217 on Monday 1.9. at 14-16

Show:

Friday, 1 August 2025, 00:01 – Wednesday, 1 August 2035, 00:01

General information about the course and labs is presented here.

Assignment	Category	Submissions	Points
Exercises: Setting up the Virtual Machine in TC217
Git Primer
NDA Agreement: FPGA lab access	Agreements	0 / 1 No submissions yet	0 / 0

Friday, 1 August 2025, 00:01 – Wednesday, 1 August 2035, 00:01

Lecture materials for the course are presented here. New slides will be added before each lecture.

Assignment	Category	Submissions	Points
Lecture 1: Introduction - Chip Implementation

Thursday, 11 September 2025, 00:01 – Sunday, 21 September 2025, 23:59
1 points required to pass the module.

Target of this exercise is to go through all the key steps of RTL-to-GDSII process flow as demonstrated in Lecture 2.

There may be changes in the assignments before the module opens!

Assignment	Category	Submissions	Points
1: RTL-to-GDSII	Labs	0 / 9 No submissions yet	0 / 5

Competition

0 / 10

Labs

0 / 45