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0 / 0 General Information
Friday, 1 August 2025, 00:01 – Wednesday, 1 August 2035, 00:01
General information about the course and labs is presented here.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| Exercises: Setting up the Virtual Machine in TC217 | |||
| Git Primer | |||
| NDA Agreement: FPGA lab access | Agreements | 0 / 1 | 0 / 0 |
0 / 0 Lectures
Friday, 1 August 2025, 00:01 – Wednesday, 1 August 2035, 00:01
Lecture materials for the course are presented here. New slides will be added before each lecture.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| Lecture 1: Introduction - Chip Implementation | |||
| Lecture 2: RTL-to-GDSII The Bare Minimum | |||
0 / 5 Opens on Thursday, 11 September 2025, 00:01 Exercise 1: RTL-to-GDSII Flow
Thursday, 11 September 2025, 00:01 – Sunday, 21 September 2025, 23:59
1 points required to pass the module.
Target of this exercise is to go through all the key steps of RTL-to-GDSII process flow as demonstrated in Lecture 2.
| Assignment | Category | Submissions | Points |
|---|---|---|---|
| 1: RTL-to-GDSII | Labs | 0 / 9 | 0 / 5 |
Competition
0 / 10
Labs
0 / 45